An example illustrating data transmission between high-speed components within a single semiconductor device, or between two devices in a communication system, is represented by the system 1 shown in FIG. 1. In FIG. 1, a transmitter 2 (e.g., a microprocessor) sends data over one or more transmission channels 4x (e.g., conductive traces “on-chip” in a semiconductor device or on a printed circuit board) to a receiver 6 (e.g., another microprocessor or memory). As a group, such transmission channels 4x are often referred to as a “data bus,” which allows one or more data signals to be transmitted from one device to another.
As discussed in U.S. patent application Ser. No. 11/873,779, filed Oct. 17, 2007, a data bus is susceptible to cross talk, simultaneous switching noise, intersymbol interference, and draws power based on the state of the data and/or frequency of data transition. One way to reduce these adverse effects and to prevent unnecessary power consumption is to encode the data. One specific form of data encoding that can be used is Data Bus Inversion (DBI).
Implementation of DBI includes encoding circuitry at the transmitter which assesses the relationship between data bits to be transmitted across a data bus and then decides (based on a particular DBI algorithm) if it would be advantageous to invert some or all of the data bits prior to transmission. If the data bits are inverted, an additional signal, referred to as a DBI bit, is also set at the encoding circuitry to indicate which data bits are inverted. Typically, as shown in FIG. 1, an extra channel 7 is then needed so that the DBI bit may be transmitted in parallel with the data bits to inform the receiving circuitry which groups of data bits have been inverted. The receiver 6 then uses the DBI bit in conjunction with decoding circuitry to return the incoming group of data bits to its original state.
One specific DBI algorithm, illustrated in FIGS. 2A and 2B, is referred to as the “minimum transitions” algorithm. While there may be variations of this technique, in general the minimum transitions algorithm begins by computing how many bits will transition during an upcoming cycle. When more than a certain number of transitions are predicted, encoding circuitry inverts the entire bus, sets the DBI bit to a specified state (high or low depending on the implementation), and drives the inverted data bits and the DBI bit in parallel across the transmission channels 4x and 7, with the DBI bit used to decode (i.e., de-invert) the inverted data bits prior to use in the receiver 6.
The minimum transitions technique can be implemented using the encoding circuitry of FIG. 2A. Because this technique is discussed at length in the above-mentioned '779 application, it is explained only briefly here. As shown, two successive bytes of data, Din<0:7> (the current byte) and Dout<0:7> (the previous byte), are compared at exclusive OR (XOR) gates 3 on a bit-by-bit basis to determine which bits in the data signals are changing. After this XOR comparison, and in accordance with DBI algorithm 9, the XOR results are summed, and a determination is made as to whether the sum is greater than four (i.e., whether there are at least five transitions from the previous byte of data to the current byte). If the sum is greater than four, the current byte is inverted before it is transmitted, and the DBI bit 7 is transmitted as ‘1.’ Alternatively, if the sum is four or less (i.e., there are no more than four transitions from one byte to the next), the data is transmitted unaltered, and the DBI bit 7 is transmitted as ‘0.’
FIG. 2B shows how the minimum transitions DBI algorithm 9 works to reduce the number of transitions in a random sequence of bytes, such that no more than four transitions are permitted between successive bytes. Again, this reduction of transitions reduces dynamic current draw at the transmitter 2 and improves the reliability of data transfer by reducing cross talk and simultaneous switching noise.
Different DBI algorithms are beneficial in different circumstances, and not all DBI algorithms are directed to minimizing the number of data transition across transmission channels. For example, other well-known DBI algorithms include the “minimum zeros” algorithm and the “minimum ones” algorithm. The purpose of these algorithms is, respectively, to minimize the number of binary zeros or binary ones transmitted across a channel. Such minimum zeros or ones algorithms conserve power when the driver or receiver circuits coupled to the transmission channels are referenced to VDDQ and VSSQ, respectively, through a resistive termination, and therefore will draw more power when transmitting or receiving a particular data state. For example, if a pull-up resistor connected to the voltage supply is used in a particular driver circuit, driving a logic ‘0’ will require more power than would driving a logic ‘1’. As a result, use of a minimum zeros DBI algorithm would be warranted. Likewise, if a pull-down resistor is used, a minimum ones algorithm would be warranted. The minimum transitions and either of the minimum zeros or ones algorithms can also be combined in a DBI algorithm, as is disclosed in U.S. patent application Ser. No. 12/015,311, filed Jan. 16, 2008. In another DBI algorithm, discussed in the above-mentioned Ser. No. 11/873,779 application, only a portion of the data bits on a bus are inverted to balance the logic states in an encoded byte across the bus, which can be referred to as a Balanced DBI algorithm. Regardless of the DBI algorithm used, all of these DBI algorithms have the common feature of sequentially receiving groups of N original data signals and selectively encoding each group to form a corresponding group of N encoded data signals while issuing at least one encoding (DBI) indicator associated with each group of the N encoded data signals.
A system 100, potentially benefiting from the implementation of DBI is shown in FIGS. 3 and 4, which is disclosed in U.S. patent application Ser. No. 12/136,868, filed Jun. 11, 2008. System 100 comprises a system for reading/writing from/to a memory set 25, which in the illustrated example comprises RAM ICs 16x. In such a system, it can be assumed for illustrative purposes that, a microprocessor 10 reads from and writes to the memory set 25, but this is merely one example and any other device or system could be used to so query the memory. In one embodiment, the RAM ICs 16x in the memory set 25 comprise dynamic RAM (DRAM) arrays of memory cells, but could also comprise static RAM (SRAM) cells, or various other types of write/erasable non-volatile memory (e.g., NAND Flash cells, Flash EPROM cells, etc.).
Intervening between the microprocessor 10 and the memory set 25 is a memory controller 12. Memory controllers 12 are well known in the art and work to create a standard interface 20 with which the microprocessor 10 can predictably communicate. The memory controller 12 couples to the microprocessor's data (DQ), address (A), and control (cntl) busses 11, and converts them to new busses 13 DQ′, A′, and cntl′ suitable for interfacing with a logic integrated circuit (IC) 14, discussed further below. Memory controller 12 typically comprises an integrated circuit separate and independent from other components in the system 100, but this is not strictly necessary, and the controller 12 could be integrated with other components if desired. A high speed differential interface between the controller 12 and the logic chip 14 may exist to improve the overall bandwidth of the system.
In the disclosed embodiment, a logic IC 14 intervenes between the memory controller 12 and the RAM ICs 16x. The logic IC 14 contains much if not all of the logic circuitry 49 typically present on a standard RAM IC. For example, the logic IC 14 can contain command decode and queuing circuitry 50. Such circuitry 50 interprets the various command signals on the cntl′ data bus (such as signals write enable (WE), row address strobe (RAS), column address strobe (CAS), and chip select (CS), assuming the RAM arrays 16x comprise DRAM memory), and issues and organizes the commands as appropriate for distribution to the RAM ICs 16x along a control bus cntl″. The logic IC 14 may also contain redundancy circuitry 52 for determining faulty memory addresses in the modified RAM ICs 16x and for rerouting around such defective addresses to functioning memory cells using programmable fuses or antifuses, as is well known. Logic IC 14 may additionally contain error correction circuitry 54, which can comprise well known circuitry for assessing and correcting faulty data in accordance with any number of error correction algorithms. Further, logic IC 14 may contain test mode circuitry 56, which is typically used during manufacturing and/or under the application of special test commands to test the operation of the various RAM ICs 16x. Typically, such circuits 50-56 are formed as part of the peripheral logic of a standard memory integrated circuit (not shown), but in the illustrated system such circuitry has been removed from the RAM ICs 16x.
System 100 can be manufactured as shown in FIG. 4, which shows the logic IC 14 and the RAM ICs 16x integrated in a multichip module 40 such that they are vertically stacked within a singular package. The bus 15 between the logic IC 14 and the RAM ICs 16x is formed using Through-Wafer Interconnects (TWIs) 83. (If the integrated circuits at issue are silicon-based, these may also be known as Through-Silicon Vias (TSVs)). As is known, TWIs 83 run though at least a portion of the logic IC 14 and through at least a portion of the modified RAM ICs 16x The TWIs 83 comprising the bus 15 are connected in series using solder bumps 84. The module 40 can likewise be affixed to the printed circuit board using solder bumps 82.
Logic IC 14 may also contain additional integration circuitry relevant to the modular integration of the RAM ICs 16x. For example, TWI rerouting circuitry 58 (FIG. 3) can assess the operation of the various TWIs 83 comprising bus 15, and if necessary can reroute around any connections deemed to be faulty. To facilitate such rerouting, and as shown in FIG. 4, some of the TWIs 83 can comprise spare TWIs 85 which are used in the event that an otherwise prescribed TWI 83 is, or has become, faulty. In this case, switching circuitry on both the logic IC 14 and the RAM ICs 16x (not shown) are used to affect the rerouting under the control of signals from the TWI rerouting circuitry 58 as is discussed in farther detail later. Circuitry and techniques for rerouting of signals on a TWI-based bus are disclosed in U.S. patent application Ser. No. 12/166,814, filed Jul. 2, 2008; Ser. No. 12/173,722, filed Jul. 15, 2008; Ser. No. 12/242,325, filed Sep. 30, 2008; and Ser. No. 11/873,118, filed Oct. 16, 2007.
As recognized in the above-mentioned '868 application, DBI can be used with the TWI-based bus 15. However, although the use of DBI can reduce power draw in a system such as system 100, it is generally not desirable to have to provide additional signaling on the bus to provide the DBI channels, such as channel from FIG. 1. In a system like that depicted in FIG. 4, the TWI-based bus 15 is already quite complicated, and can comprise hundreds to thousands of TWIs 83. To add additional TWIs 83 to carry the DBI signals takes up space and adds complication to the design and manufacture of the module 40.
Nevertheless, the inventor believes that advances in system integration as exemplified by system 100 are making the implementation of DBI, and other data encoding algorithms, more attractive. At the same time, the use of such algorithms is becoming more important as systems shrink and as it becomes increasingly important that such systems reduce their power consumption and operate at high speeds. The inventor believes that it would be desirable to include DBI in a system such as system 100, without adding additional TWI-based channels to carry the DBI signals.